library ieee;
use ieee.std_logic_1164.all;

entity adder8 is
port(
	input : in std_logic_vector(7 downto 0);
	cin   : in std_logic;
	cout  : out std_logic;
	sum   : out std_logic
	);
end;

architecture behave of adder8 is


component adder1 
	port(
	a,b,cin : in std_logic;
	cout,sum  : out std_logic
	);
end component;

signal Q : std_logic_vector(7 downto 0);
signal P : std_logic_vector(7 downto 0);

begin
	process(input,cin) begin
		cout <= Q(6);
		sum  <= P(6);

	end process;

A1 : adder1 port map(a=>input(0),b=>input(1),cin=>cin,cout=>Q(0),sum=>P(0));
A2 : adder1 port map(a=>input(2),b=>P(0),cin=>Q(0),cout=>Q(1),sum=>P(1));
A3 : adder1 port map(a=>input(3),b=>P(1),cin=>Q(1),cout=>Q(2),sum=>P(2));
A4 : adder1 port map(a=>input(4),b=>P(2),cin=>Q(2),cout=>Q(3),sum=>P(3));
A5 : adder1 port map(a=>input(5),b=>P(3),cin=>Q(3),cout=>Q(4),sum=>P(4));
A6 : adder1 port map(a=>input(6),b=>P(4),cin=>Q(4),cout=>Q(5),sum=>P(5));
A7 : adder1 port map(a=>input(7),b=>P(5),cin=>Q(5),cout=>Q(6),sum=>P(6));

end;